The Phase-Shifted Full-Bridge (PSFB) topology is a DC-DC converter
with the potential to meet future power efficiency requirements. The flexibility of the DSC makes the unstable PSFB topology easier to manage and enables advanced technologies that further improve PSFB efficiency.
Below we will discuss the simple full-bridge topology necessary for high-frequency operation and then discuss the efficiency improvement strategy.
Full bridge converter
As shown in Figure 1, the full-bridge converter is configured with four switches (Q1, Q2, Q3, and Q4). When the diagonal switches Q1, Q4 and Q2, Q3 are simultaneously turned on, a complete input voltage (VIN) is provided across the primary winding of the transformer. In each half cycle of the converter, the diagonal switches Q1 and Q4 or Q2 and Q3 are turned on, and the polarity of the transformer is reversed every half cycle. In a full-bridge converter, the switching current and primary current at a given power will be halved compared to a half-bridge converter. This current reduction makes full bridge converters suitable for high power levels. However, diagonal switches use hard switches that cause high switching losses when turned on and off.
In the past, power engineers had to use less efficient hard-switching power conversion methods because the right controllers had not yet appeared. The losses of these methods increase with increasing frequency, thus limiting the operating frequency, which in turn limits the ability of the power supply to supply power efficiently.
Figure 1: Full Bridge Converter
Soft Switch Full Bridge (PSFB) Topology
With existing DSCs, designers can now consider using higher operating frequencies to reduce the number of magnetic and filter capacitors in the power supply. An increase in frequency can result in higher switching losses in hard switching power converters such as conventional full bridge converters. A better alternative is to choose a relatively complex soft switching method to reduce switching losses and provide higher power density.
The PSFB converter is a soft switching topology that uses parasitic capacitance (such as the output capacitance of switching devices such as MOSFETs and IGBTs) and the leakage inductance of the transformer to achieve resonant conversion. This resonant transition allows the switching device to have zero voltage across it when turned on, thereby eliminating switching losses when it is turned on.
PSFB converters have been widely used in telecom and server applications where converter power density and frequency are critical. The regular work of PSFB converters is covered in many articles, and we will show how DSC can further improve performance.
Figure 2: Phase-shifted full-bridge converter
Phase-Shifted Full-Bridge Converter with Traditional Synchronous MOSFET Gate Drive
Most DC-DC converters are designed with isolation transformers to ensure user safety and compliance with regulations established by regulatory agencies. The higher rated power supply has a PSFB topology in the primary design and a full wave synchronous rectifier in the secondary design for higher efficiency.
In the PSFB converter, if the synchronous MOSFET configuration controlled by the conventional method is used, Q1, Q3 or Q2, Q4 of the MOSFET should be in an on state. At this time, no power is transmitted from the primary to the secondary, and the MOSFET Q5 is still in an on state.
Since there is an inductance (Lo) on the secondary side of the converter, the energy in the output inductor circulates between the MOSFET Q5 and the secondary winding of the transformer (Tx). Current continues through the secondary winding of the transformer through the MOSFET's channel or through the internal diode of the MOSFET. Since current will be reflected from the secondary to the primary, there will be a circulating current during the primary zero state (primary to secondary without any energy transfer), which can result in losses in the converter. These loop losses are especially noticeable at higher voltages than in the case of rated input voltages. In addition, to avoid transconductance, a dead zone is intentionally introduced between the Q5 and Q6 MOSFET gate drivers. During this time, any synchronous MOSFET will not turn on. Therefore, current will flow through the internal diode of the MOSFET. These MOSFET internal diodes have a high forward voltage drop compared to the MOSFET's Rds(ON), which is (VF * I) (I2rms*Rds(on)).
By superimposing the gate drive signal, high losses can be prevented in conventional synchronous gate drive, which will be described in the next section.
Figure 3: Traditional configuration of synchronous MOSFET gate drive
Superposition of synchronous MOSFET gate drive signals
By superimposing the PWM gate drive signal of the synchronous MOSFET, losses can be avoided during the zero state of the primary side of the transformer. This will improve power efficiency in the following three areas.
First, in a center-connected full-wave rectifier, superimposing the gate drive signal of the synchronous MOSFET will eliminate the flux in the secondary center tap of the transformer, so that there is virtually no flux between the transformer secondary and the primary.
Second, the two synchronous MOSFETs and the two transformer center taps are turned on simultaneously, rather than one synchronous MOSFET and one central tap transformer. Therefore, the secondary current will have only half of the effective resistance, and the loss will be reduced by half compared to the case where only one synchronous MOSFET is turned on.
Figure 4: Superimposing the synchronous MOSFET gate drive signal to increase efficiency
Finally, in conventional switching methods, the intentionally introduced deadband may be 10% of the switching period, and during this deadband, high secondary current will flow through the high forward voltage drop internal diode of the MOSFET. By configuring the PWM gate drive signal stack of the synchronous MOSFET, high secondary current can flow through the MOSFET channel. In this case, there will be only Rds(ON) losses, which are very small compared to the losses caused by the internal diodes of the MOSFET in the deadband. For systems with telecom input (36 to 76 VDC), the efficiency of the DC-DC converter is increased by 3-4% by superimposing the synchronous MOSFET gate drive signal.
Implementing these technologies requires flexible power controllers with fully independent PWM outputs. DSCs such as the dsPIC DSC provide flexibility and PWM peripherals to easily implement this and other efficiency-enhancing technologies.
The PSFB topology has the potential to achieve the efficiency required by modern power supplies. Digital control allows designers to control the PSFB topology very accurately and implement advanced control techniques such as superimposing synchronous MOSFETs. New topologies, new technologies and new ideas are driving power into the 21st century. Digital controllers, such as Microchip's dsPIC DSC, are ready for future power needs.