ECRI Microelectronics

Design of Transient suppression High Power DC DC Converter

Design of  Transient suppression High Power DC DC Converter 

 Abstract: This article introduces design scheme of a transient suppression high power DC DC converter. The design principle and the key technology are analyzed, and the design simulation and experiment are implement. At last, the main technical specification and test results are given.
Keywords: high power, transient suppression,efficiency, wide input voltage range, simulation

1 Introduction 
As our weapon system developing and aircraft system increasing its performance, the requirement of matched components is higher and higher. According to the request for GJB181 aircraft power supply system, DC DC converters meet the demand of the 80V/50ms input voltage surge suppression.
The article introduces a 50W DC DC converter with 16-40V input and 5V isolated output. Besides, we study the key technology of the transient suppression high power DC DC converter through the angle of designing the circuit and compare the product’s simulated analysis with performance. The product uses the simple-end forward topology so that it has advantages of high output voltage accuracy, low voltage regulation, low load regulation, high reliability and functions of forbid-dance, under-voltage and short-circuits protection.
2 The design of the transient suppression high power DC DC converter
The DC DC converter has to meet the demands of 80V/50ms input voltage transient suppression through GJB181. During applying the DC DC converter practically, there are two definitions of surge suppression: One is stopping hurt DC DC converter in surge voltage. Another is making DC DC converter work normally in surge voltage. To charge the aircraft system stably and keep post load work normally during the 80V/50ms surge voltage, the DC DC converter is created for meeting the requirement of operating normally with 80V/50ms surge voltage.
2.1 The technology of 80V/50ms transient suppression DC DC converter
There are two ideas in the design of the transient suppression DC DC converter: One is using the input voltage clamping to stop surge voltage influence DC DC converter of which disadvantage is ineffective. Another is making transient suppression DC DC converter resist high surge voltage which the article applied.

There are three problems when we are designing the transient suppression DC DC converter:
(1)The parts of input filter and auxiliary power supply: The 80V input voltage directly acts on
the input filter capacitor and auxiliary charged triode. To ensure the reliability of the power supply modules, we choose the device with the voltage proof meeting the derating demand. Due to the high voltage-proof input capacitor with big size, we need to adjust layout design.
(2)The part of changing the power: When the input voltage is 80V, the MOSFET voltage stress increases at least 40V and the output rectifier Schottky diode voltage stress increases at least 20V. That pushes us to choose MOSFET and Schottky diode with higher voltage-proof. And we also need to take measure for the high power loss of MOSFET and Schottky.
(3)The part of the transformer and feedback control: When the input voltage is 80V, the transient suppression DC DC converter’s duty ratio is small. That will make loop circuit unstable. And we need to increase the duty ratio with slope compensation circuit and stabilize the circuit with suitable feedback network and circuit’s zero pole.
2.2 Studying the efficiency
To make the converter bear 80V/50ms surge voltage, we choose many power devices with high voltage resistance whose Ron is large and Ton is long. Because the converter in 80V/50ms surge voltage will reach to voltage spike on the power device, and that will decrease the product’s efficiency, so to avoid them, we need to improve the product. There are three aspects of the internal loss in switching power supply: switching loss, conducting loss and other loss.
The switching loss is that at the moment of the device’s on-off, the switch has stray capacitance and parasitic inductance which stop the voltage and current abruptly changing, then the voltage and current alternating on the switch form the switching loss.
To decrease the switching loss, there are several ways:
(1) Accelerating the speed of turning on or off the drive waveform and decrease the switching loss. The figure 2(a) shows the totem-pole drive circuit composed of the triodes including NPN and PNP. When the drive circuit is added, the speed of the MOS grid’s rising edge and failing edge is quicker. We can see them in figure 2(b). At that time, the MOSFET’s switching loss is apparently decreasing.

Figure 2(a) The drive circuit

Figure 2(b) The MOS grid’s waveform of adding drive circuit back and forth

(2) Adding RC on the MOSFET and Schottky diode to absorb network and dealing with the peak gently can partly decrease the power tube’s switching loss and increase circuit’s reliability.
The conducting loss is that when the device is working, the drive and the waveform are stable, the conducting loss is coming from the turning-on power switch. The conducting loss can be I2dRdsRds(OH).
(1) We connect two small volume MOS in parallel, decrease MOSFET conducting resistance and conducting loss.
(2) We connect two output rectifier Schottky in parallel, decrease Schottky conducting resistance and conducting loss.
Besides, we take measure below to decrease other loss in the circuit and increase the efficiency:
(1) We offer controlling chips the supply voltage by using the feedback winding (inductor sample). After the circuit completely starts, we use the feedback winding to replace auxiliary supply triode for charging the chips so that the static power loss on the auxiliary supply triode is going to be small.
(2) We use the current transformer sample instead of resistor sample. The structure of the current transformer sample is shown in the figure 3. Both the secondary coil and primary coil are on the same closed iron core whose current ratio is equal to turns ratio. The current transformer has complex circuits but low energy consumption and good signal reducibility. It can isolated controlling circuit from main circuit and effectively increase circuit efficiency as well as ensure the circuit’s every index meet the requirements. The sampling circuit is shown in the figure 4.

Figure 3 The model of the current transformer
The loss of the sampling instrument transformer includes copper loss and iron loss. The iron loss can be ignored. The copper loss is  n is the ratio of primary and secondary coils of the current transformer. Iin is input current. If we use the traditional sampling resistor, the loss on the sampling resistor is I2inRsense. Because Rrms and Rsense are all rank of mΩ, we can get that the loss on the transformer is much smaller than the loss on the sampling resistor.

Figure 4 The current transformer sampling circuit
(3) We choose sandwiched winding to decrease transformer’s leakage inductance peak and skin effect so that the sum of copper loss, iron loss, skin effect, proximity effect and eddy-current loss is smallest.
2.3 The design of wide input range
(1) The slope compensating skill
Because the converter is asked for working stably under the 80V/50ms surge voltage, when the input voltage is 16V, the transient suppression DC DC converter’s duty ratio is over 0.7. To stop the second harmonic generation happening when circuit’s duty ratio D is over 0.5, the slope compensating circuit is added. The principle of the slope compensation circuit is shown in the figure 5. We add a compensating circuit with the slope of -m(m>0) to the induced voltage from inductive current through the slope compensating circuit for getting stable inductive current waveform.
The converter uses the compensating way of the emitter follower which is shown in the figure 5. PWM oscillator signal is added to the peak current sampling through triode and resistor, with triode’s amplification, to increase the compensating network’s equivalent resistance for decreasing the influence from compensating network to working frequency.

Figure 5 The emitter follower’s slope compensating circuit
Meanwhile, when the 80V/50ms surge voltage is passing, to ensure the loop’s stability, a small capacitor is shunted between 3 and 4 of PWM. We adjust PWM’s 3 waveform to avoid that the low duty ratio makes interference voltage disturb compared end.
To ensure the transformer work stably under the 16-40V input voltage and 80V/50ms, the converter’s max duty ratio Dmax=0.75.
(2) The design of the transformer
The converter uses the magnetic tank with forward topology, 50W power and the 22mm2 chosen magnetic core’s effective cross-sectional area Ae. It also chooses big magnetic flux △Bmax and low loss magnets. Because the circuit’s max duty ratio is bigger than 0.5, to ensure work stably in the input range, the max duty ratio Dmax is regarded as the design basis. The transformer’s design process of the main parameters is shown in the figure 6:

Figure 6 The transformer’s design process of the main parameters
In the figure 6: Ae is the magnetic core’s effective cross-sectional area; VIN(min) is the min input voltage; △Bmax is the max working magnetic flux density; Dmax is the max duty ratio; T is the converter’s work period. 
(1) The primary number of turns and wire diameter
When the low end 16V is inputting, the system’s duty ratio is max. According to the Faraday's law of induction formula we can get the number of turns of the transformer’s primary coils:

(2) The secondary number of turns and wire diameter

According to the principle of the forward converter, the input and output voltage is:
Us is Schottky’s forward voltage drop which is 0.15V. If the low end 16V is inputting, the duty ratio is 0.75 and the primary coils’ number of turns is 6, then we can use the formula: Ns=3.22
Considering the efficiency, the final chosen turn ratio is 6:3.
3 The simulation analysis and the result of the product validation
We use Saber to do the simulation analysis on the product of 50W single 5V/10A. On the conditions of different input voltage and load current, the converter works stably, the duty ratio and the theoretical design is similar, the waveforms of the MOSFET and Schottky are similar with the theoretical calculation. That means the theoretical analysis is verified.
3.1 The output voltage of the transient suppression DC DC Converter
When the 28V full load is inputting, the output voltage waveform is shown in the figure 7, the simulation waveform conforms to the real wave. The waveforms of the input current and output voltage are stable and work quickly.

Figure (a) The simulation waveform

Figure (b) The real waveform
3.2 The waveforms of the MOSFET drain-source and Schottky
MOSFET drain-source voltage VDS and grid voltage VGS are shown in the figure 8 and 9. The secondary Schottky waveforms are shown in the figure 10 and 11.
From the figure 8 to 11, we can see that the converter work stably in the whole voltage input range. The low-end duty ratio is 0.75 and the high-end duty ratio is 0.29. Because of the existence of the real product’s the leakage inductance of transformer and part parasitic parameters in the loop, there are several differences between the simulation waveform and the real wave. But the converter’s working position and voltage stress are mutually corresponding, the devices are meeting the derating requirement and the working position is stable.

Figure(a) 16V full load

Figure(b) 28V full load

Figure(c) 40V full load
Figure 8 The simulation waveform of MOS’s VDS and VGS

Figure(a) 16V full load

Figure(b) 28V full load

Figure(c) 40V full load
Figure 9 The real waveform of MOS’s VDS and VGS

Figure(a) 16V full load

Figure(b) 28V full load

Figure(c) 40V full load
Figure 10The simulation waveform of Schottky

Figure(a) 16V full load

Figure(b) 28V full load

Figure(c) 40V full load
Figure 11 The real waveform of Schottky
3.3 The change of the load step
When the input voltage is nominal value, the load from full to half and from half to full will cause output voltage change accordingly. They are shown in the figure 12. The load step’s simulation waveform and real wave are similar and meet the index’s requirements. The recovery time of the load step is the condition when the output voltage gets back to the 1% stable value. The load step’s simulation and real results are similar and meet the index’s requirements.

Figure(a) The simulation waveform

Figure(b) The real waveform

Figure 12 The load step waveform
3.4 The input step waveform
    When the load is full, the input voltage is from the min to the max and from the max to the min, the output voltage waveform is shown in the figure 13. The recovery time of the output step is the condition when the output voltage gets back to the 1% stable value. The output step’s simulation and real waveforms are similar and meet the index’s requirements.

Figure(a) The simulation waveform

Figure(b) The real waveform

Figure 13 The input step waveform
4 Conclusion 
On base of studying the transient suppression high power DC DC converter, the article analyzes its surge suppression, efficiency enhancers and wide input range. With the sufficient theoretical research, simulated analysis and reliable prediction, the actual indexes of the product called 5V/10A single transient suppression we designed meet all requirements. It also verifies the feasibility of the technical route, the accuracy of the theoretical design and the reliability of the simulated analysis.

Reference:
[1] Abraham I. Pressman,Keith Billings,Taylor Morey,Switching Power Supply Design, Beijing; Publishing House of Electronics Industry, 2010.
[2] Zhang Zhan-song, Cai Xuan-san, The Principle and Design of the Switching Power Supply, Publishing House of Electronics Industry, 1998.
[3] Marty Brown. The Guide of Designing the Switching Power Supply. Mechanical Industry Press, 2004.
Relate News