Resolver to Digital Converters (HSDC/HRDC1459 Series)

2. Scope of application of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)

Military servo control system; antenna monitoring; radar control system; navigation system for naval vessels; cannon control system; flight instrument system; aviation electronic system; computerized numeric control (CNC) machine; robot technology.

3. General of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)

HSDC/HRDC1459 series synchro/resolver-digital converter is a hybrid integrated conversion device for continuous tracking designed on the principle of model II servo. This series products are designed and manufactured by MCM process, the core elements adopt special chip developed independently by our institute. The pin arrangement is compatible with SDC14560 series products of American DDC company, 16-bit parallel natural binary code data latch output, 36-line DIP totally sealed metal package, have the advantages of high precision, small volume, low power consumption, light weight and high reliability etc., and can be widely used in important strategic and tactic weapons such as aircraft, naval vessel, cannon, missile, radar, tank, etc.

4. Electric performance (Table 1, Table 2) of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)

Table 1  Rated conditions and recommended operating conditions

Note: * indicates it can be customized as per user’s requirement.

Table 2  Electric characteristics

5. Step response of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)
When a step or initial power-on happens in the input signal, the response will be inhibited due to the limitation of maximum tracking speed. The oscillation process of the output digital angle is shown in Fig. 2:

6. Operating principle (Fig. 3) of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)

These two signals and the digital angle φ of internal reversible counter are multiplied in the multiplier of Sine and Cosine functions and are error treated:
KE0sin (ωt+α)(sinθ cosϕ-cosθ sinϕ), i.e. KE0sin (ωt+α) sin(θ-ϕ)
The signals are sent to voltage controlled oscillator after amplification, phase discrimination and integration filtration, if θ-φ≠0, the voltage controlled oscillator will output the pulses, and the reversible counter counts, till θ-φ becomes zero within the accuracy of the converter, during this process, the conversion tracks the change of input angle all the time.
Reading method:
Following two methods are available for data transfer:

(1)  Inhibit method:
After 640ns of logic low, the output data is valid, and the converter realizes data transfer through and . After Inhibit  is released, the system will automatically generate a pulse with width equal to the busy pulse for data updating.


Fig.4 Time sequence of data transfer

(Note: according to GJB/Z299B-98, envisaged good ground condition)
Table 3  Pin designation

Lower 8-bit digit enabled signal input, this pin is the logic input pin of data gating control, its function is to carry out three-state control externally on the lower 8-bit output data of the converter. Low level is valid, the lower 8-bit output data of the converter occupies the data bus; At high level, the pin of lower 8-bit output data is in high resistance state, and the device does not occupy the data bus. Enable and release delay time is 600ns(max).
higher 8-bit digit enabled signal input, this pin is the logic input pin of data gating control, its function is to carry out three-state control externally on the higher 8-bit output data of the converter. Low level is valid, the higher 8-bit output data of the converter occupies the data bus; At high level, the pin of higher 8-bit output data is in high resistance state, and the device does not occupy the data bus. Enable and release delay time is 600ns(max).
Inhibit static signal input, this pin is the input pin of control logic, its function is to output data externally to the converter to realize optional latching or bypass control. At high level, the output data of the converter directly outputs without latching; at low level, the output data of the converter is latched, the data is not updated, but the internal loop is not interrupted, and tracking is operating all the time, Inhibit has connected pull-up resistance internally. After 600ns (max) delay of descending edge of static signal, the data becomes stable (whether the device occupies the data bus, i.e. when does it output the data depends on the state of and ).
CB “Busy” signal output, this signal indicates whether the binary code output of the converter is valid or not. When the change of angle input reaches 0.33 angular minute, CB end outputs a positive pulse with a width of 400ns(typical). When CB is at high level, it indicates the converter is carrying out data conversion, the data output at this time is invalid; after 600ns (max) delay of descending edge of CB signal, the data becomes stable and the updated data output at this time is valid.
bit fault detection bit output, high level indicates normal operation of the converter, in the event that the signal wire is broken or the converter fails to track normally, this bit changes into low level from high level.
RIPCLK zero-bit signal input, when the output data increment to all “0” from all “1” or decrement from all “1” from all “0”, a positive pulse with a width of 200us is output.
VL, +VS, -VS Incoming terminal of power supply

GND  Ground wire incoming terminalReference signals are connected to RHi and RLo. In the case of synchro, signals are connected to S1, S2, and S3 as per the following conventions.

Notes:

• Pin voltage shall not exceed 20% of rated value.
• The voltage of power supply shall not exceed the specified range.
• Do not connect reference RHi and RLo to other pins.
• For the power supply connected to +VS and -VS pin, its voltage shall be ±15V, and shall not be reversely connected. The digital logic power supply VL is connected to +5V. Between the power supply and ground, 0.1µF ceramic capacitance and 6.8µF electrolytic capacitance shall be connected in parallel.
• Reference signals are connected to RHi and RLo. In the case of synchro, signals are connected to S1, S2, and S3 as per the following conventions.

• In the case of resolver, signals are connected to S1, S2, S3 and S4 as per the following conventions:

Pins of CB, shall all be connected as described for the above data transfer.

9. Table of weight values(Table 4) of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)

Table 4  Table of weight values

10. Connection diagram for typical application (Fig. 7) of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)	11. Package specifications (unit: mm) (Fig. 8, Table 5) of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)
Fig. 7 Connection diagram for typical application	Fig.8 Outside view and dimensions of package

Table 5  Case materials

Case model	Header	Header plating	Cover	Covering plating	Pin material	Pin plating	Sealing style	Notes
UP4820-36A	4J42	Ni plating	4J42	Chemical Ni plating	4J42	Au plating	Matched seal	Header plus three solid glass beads

12. Part numbering key (Fig. 9) of Synchro to Digital Converters or Resolver to Digital Converters (HSDC/HRDC1459 Series)

Fig.9 Part numbering key

Note: when the above signal voltage and reference voltage (Z) are non-standard, they shall be given as follows:

(e.g. reference voltage 5V and signal voltage 3V are expressed as -5/3)

Application notes:
Supply the power correctly, upon power-on, be sure to correctly connect the positive and negative pole of the power supply for fear of burnout.
Upon assembly, the bottom of the product shall fit to the circuit board closely so as to avoid damage of pins, and shockproof provision shall be added, if necessary.
Do not bend the pinouts to prevent the insulator from breaking, which affects the sealing property.