Resolver to Digital Converters (MSDC/MRDC37 series)

1. Features of Synchro/Resolver-Digital Converter (MSDC/MRDC37 series)(for outside view, see Fig. 1) 

2. Application of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)

Servo mechanism; antenna monitoring; navigation system; cannon control; industrial control; robot system; radar control system.

3. Description of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)

MSDC/MRDC37 series are 16-bit digital to synchro or digital to resolver converters. The input signal is divided into four-wire resolver and excitation signal or three-wire synchro and excitation signal. The output signal is parallel natural binary code buffered through three-state latch and compatible with TTL level.
The product applies second-order servo circuit with small size and light weight,  and the user can use it very conveniently by controlling signal pins.

Table 2  Rated conditions and recommended operating conditions
Note: * indicates it can be customized as per user's requirement.

Table 2  Electric characteristics

Note: ① the tracking speed is 3 rps for 16-bit resolution and 36 rps for 12-bit resolution; St can be designed according to the user’s requirement.

4. Operating principle of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series) (Fig. 2)

The synchro input signal (or input signal of resolver) is converted into the orthogonal signal through internal differential isolation:

Fig.2  Block diagram for operating principle

Where, θ is analog input angle
These two signals and the digital angle φ of internal reversible counter are multiplied in the multiplier of Sine and Cosine functions and are error treated:



The signals are sent to voltage controlled oscillator after amplification, phase discrimination and integration filtration, if θ-φ≠0, the voltage controlled oscillator will output pulse to change the data in the reversible counter, till θ-φ becomes zero within the accuracy of the converter, during this process, the converter tracks the change of input angle θ all the time. For the block diagram of working principle, see Fig. 2.

Transfer function of the converter is shown in Fig. 3. Closed-loop function




Fig. 3  Function transfer of the converter

 Inhibit Methods of data transfer and time sequence
There are two methods for reading the effective data in the converter: synchronous reading and asynchronous reading.
(1) Inhibit method (synchronous reading):
A: the converter is connected with 16-bit bus. Bysel is connected with logic "1".
Set Inhibit from logic "1" to logic "0" (data lock), and wait for 1μs; set Enable to logic "0" to allow the latch in the converter to output data; read 12-bit, 14-bit or 16-bit data; set Inhibit to logic "1" in order to get ready for reading the next effective data (Fig. 4);
B: the converter is connected to 8-bit bus, D1~D8 bit are connected to data bus, and the rest are empty.
Set Inhibit from logic "1" to logic "0" (data lock), and wait for 1μs; set Enable to logic "0" to allow the latch in the converter to output data; set Bysel to logic "1", directly read the high 8-bit data, set Bysel to logic "0", read the data in other bits with automatic zero padding in the vacant bits; set  to logic "1" in order to get ready for reading the next effective data (Fig. 5).
Inhibit

Fig4  Time sequence of 16-bit bus transfer                                       Fig5  Time sequence of 8-bit bus transfer

(2) Busy method (asynchronous reading):
In asynchronous reading mode,  is set Inhibit to logic "1" or empty, whether the internal loop is always in the stable state or whether the output data is valid shall be determined through the status of busy signal Busy. When Busy signal is at high level, it indicates the data is being converted, and the data at this time is unstable and invalid; when Busy signal is at low level, it indicates the data conversion has been completed, and the data at this time is stable and valid. Once high level occurs in Busy during reading, the reading at this time is invalid. In asynchronous reading mode, the Busy output is pulse train of TTL level, its width depends on its rotational speed, there are also two use methods of the bus, i.e. 8-bit and 16-bit, the data reading during effective data output is also controlled by Enable , please refer to the time sequence diagram for data transfer (Fig. 6 and Fig. 7).


Fig.6  Time sequence diagram for 16-bit bus transfer Fig.7  Time sequence diagram for 8-bit bus transfer

Status signal pins: Busy, DIR, R, C.
When the input of the converter changes, Busy outputs a train of pulses of CMOS level, its frequency is determined by the highest rotational speed. When Busy is at high level, it means the second-order servo circuit in the converter is operating, the data at digital output end is changing; on the contrary, the computer can directly read the data.
DIR signal is used to indicate forward/reverse rotation. When the output code is up count, the output is high level; when the output code is down count, the output is low level.
Zero signal output R.C: when the output data increments from all "1" to all "0", or the output data decrements from all "0" to all "1", the output is positive pulse, the pulse width is 200μs.

5. MTBF curve of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)(Fig. 7)

Fig. 8  MTBF-temperature curve
(Note: as per GJB/Z299B-98, envisaged good ground condition)

6. Pin designation of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)(Fig. 9, Table 3)

Fig.9  Pin designation (top view)

Table 3  Pin designation


Notes: S1, S2, S3, S4 are signal input of synchro to digital converters or resolver to digital converters, and S4 is left unconnected for synchro;
D1~D16 are binary data output, for MSDC/MRDC3752 series converter, pin 13, 14, 25 and 26 are left unconnected;
for MSDC/MRDC3754 series converter, pin 25 and 26 are left unconnected.

7. Table of weight values of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)(Table 4)

Table 4  Table of weight values

8. Connection diagram for typical application of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)(Fig. 10 and Fig. 11)

Note: the supply voltage shall not exceed the specified range; do not connect reference RHi and RLo to other pins.

9. Package specifications (unit: mm) of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)(Fig. 12)

Fig. 12 Outside view and dimensions of package

10. Part numbering key of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series)(Fig. 13)

Fig. 13 Part numbering key
Note: when the above signal voltage and reference voltage (Z) are non-standard, they shall be given as follows:




(e.g. reference voltage 5V and signal voltage 3V are expressed as -5/3)

Application notes of Synchro to Digital Converters or Resolver to Digital Converters (MSDC/MRDC37 series):

• Supply the power correctly, during the power-up, accurately connect the positive and negative poles of power to avoid burnout.
• When the max. absolute rating value is exceeded, the device may be damaged.
• Upon assembly, the bottom of the product shall fit to the circuit board closely so as to avoid damage of pins, and shockproof provision shall be added, if necessary.
• When the user places an order for the product, detailed electric performance indexes shall refer to the relevant enterprise standard.